RTL to GDSII
Overview
The customer is a Tier 1 Semiconductor Company from Automotive industry based out ofNorth America. The customer was looking for RTL2GDSII implementation team for multiplechips where they required a delivery team of 60 members for schedule, risk estimation, andquality signoffs.
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Challenges
AI Core, GPUs, VLIW DSPs, Graphics Accelerators, Image Processing Engines, Embedded Vision Engines
PCIe, USB2/3, DDR3 and other standard Peripherals
Leading Edge node
Synthesis Strategy for best PPA : Constraint development & maturity
Timing Closure using Ageing Corners
Application Validation and Verification Coverage
Outcomes
- IP verification, Soc Verification, DFT implementation and coverage, including fault coverages
- IP constraint understanding integration, interactions with RTL team
- RAM tiling strategy definitions, Multibit Register handling, Optimal Channel Length and VT selections
- DFT and Functional clocking aware constraint development
- RC Spread & Ageing aware CTS & data path closure methodology tweaks
- Hardware redundancy on processor core with split/lock mode
- ECC on critical RAMS
- LBIST on critical logics
- On time Delivery, First Pass Success
