RISC-V architecture is an open standard ISA that breaks free from traditional proprietary architectures, empowering industry and academia alike to enter the chip design area. From established semiconductor giants to innovative startups, RISC-V is democratising access to processor design, fostering unparalleled innovation and competition.
Delivering reliable and bug-free processors is essential for any RISC-V company. Silicon recalls are cost-heavy and detrimental to an emerging RISC-V market. Thorough and meticulous verification helps uncover even the most obscure bugs before production, ensuring high design quality minimizing post-launch issues and driving time-to-market decisions.
Webinar Highlights
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RISC-V Architecture and Micro-architecture
Learn the architecture and its implementation details from a verification point of view.
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Processor Verification
Learn how any processor implementation is verified and its challenges
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Scope of RISC-V Verification
Understand the whole verification space for the ISA implementation.
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Coverage Closure Metrics
Learn about the components of verification closure
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Tools for Verification
Gain insights into different tools and methodologies for meeting coverage requirements
On-demand Webinar Ideal For
- Hardware Design or Verification Engineers
- Technology Enthusiasts
- Students and Academicians
- Industry Professionals
Don’t miss this chance to understand how design quality is met in today’s community-driven collaborative RISC-V ecosystem.
Speakers
Lavanya Jagadeeswaran
Founder and CEO
Vyoma Systems
Lavanya is the Founder and CEO of Vyoma Systems. She has over 13 years of experience across various processor teams. Lavanya has been part of IBM (IBM Z processors), ARM (ARM Cortex M processors) processor verification teams and led the RISC-V processor verification efforts at Rambus Chip Technologies and SHAKTI Group at IIT Madras. She led the verification efforts for RISC-V processors and holds an MS in Computer Science and Engineering from IIT Madras, India.
Poornima S P
Architect Verification Engineer
ACL Digital
Poornima S.P. is a highly skilled Design Verification Engineer with over 18 years of experience in chip development. Her expertise encompasses SystemVerilog, UVM, and formal verification methodologies, with a strong foundation in cache coherency and hardware trace analysis. With a successful 16+ year tenure at IBM and her current leadership role at ACL Digital, she brings deep knowledge and proven success in RISC-V core development for cluster-based SoCs, interfaces, and peripherals in ML-based SoCs using C tests in UVM environment, and vector processing for streaming data.