One of the main attractions of the RISC-V standard is that it is open source and does not involve paying license fees or royalties, resulting in a lower cost of silicon production. However, the design and implementation of any System on Chip (SoC) require the integration of several engineering aspects, including CPU architecture, SoC design and verification, physical implementation, Electronic Design Automation (EDA) tools/libraries, software (SW) tools, foundries, and silicon packaging. Engineering teams need to comprehend each aspect of this chain from the standpoint of the RISC-V standard to build a successful product that minimizes overall development costs.
ACL Digital engineers possess a comprehensive understanding of various aspects of silicon engineering. Our robust team, equipped with experience in CPU architecture, design, and physical implementation, amalgamates the diverse skills required for designing and implementing a System on Chip (SoC) based on RISC-V.
Webinar Highlights
- Recent trends in RISC-V ISA/processor cores
- Developments in RISC-V tools for software and hardware development
- Survey of RISC-V ecosystem organizations and focus areas
- Overview of commercial hardware/IP providers
Who should attend the webinar
- Individuals interested to learn more about the RISC-V ecosystem and the stakeholders involved
- Engineers and developers looking to familiarize with EDA / SW tool options for RISC-V-based systems
- Program managers handling end-to-end project management for RISC-V-based SoC development
- Product developers exploring options to manufacture RISC-V-based SoCs
Speaker
Ramesh Parthasarathi
Director - RTL Design
Bringing more than two decades of expertise in semiconductor design, Ramesh Parthasarathi excels in SoC Design, Integration, and Implementation. With a comprehensive background in handling diverse IPs and SoCs, mainly designed for embedded applications, wireless devices, and consumer electronics, Ramesh deeply understands frontend design challenges and backend implementation intricacies.
As Director of RTL Design at ACL Digital, Ramesh leads with a visionary approach. His leadership style is marked by a commitment to excellence, driving the team towards innovative solutions in the ever-evolving landscape of semiconductor design. Ramesh's passion and extensive experience make him a vital leader, driving success and advancements in cutting-edge technologies.